For mounting multipin LSI packages to prepare MPUs, gate arrays or the like onto printed wiring boards, a flip chip mounting method has hitherto been adopted in which conductive projections (bumps) made of eutectic solder, high-temperature solder, gold or the like are formed on a connection pad part at a circuit surface side of a semiconductor chip (hereinafter referred as a chip or chips) and are confronted with and are brought into contact with corresponding terminal parts on a chip mounting substrate by so-called “facedown method” for melt/diffusion bonding. However, in this method, when exposed to a periodical temperature fluctuation, there is a possibility that the joint may brake due to the difference of a thermal expansion coefficient between the semiconductor chip and the chip mounting substrate. Thus, a method is proposed which comprises injecting a heat curable liquid resin (an underfill material) into a gap between the whole circuit face area of the semiconductor chip connected in a facedown state provided with the bump electrode and a chip mounting board opposing thereto; and then curing the heat curable liquid resin to bond the whole face of the bump joint portion to the chip mounting substrate. Thereby the thermal stress focused on the bump electrodes is dispersed to prevent the breaking. However, the gap between the semiconductor and the chip mounting substrate in the flip chip mounting, is as small as 40 to 200 μm. This causes to take considerable amount of time during the step of filling the underfill material without forming any voids; and viscosity control between the lots of the underfill material is complicated. Also, the amount of the underfill material to be filled is inconsistent which causes the quality of the product to vary.
In order to overcome these problems, for example, Patent document 1 (Japanese Patent Laid-Open No. H09-213741), Patent document 2 (Japanese Patent Laid-Open No. H10-242208), Patent document 3 (Japanese Patent Laid-Open No. H10-270497), and Patent document 4 (Japan Laid-Open No. 2002-118147) propose a technique in which a sheet-like heat curable resin or a thermoplastic resin are sandwiched between a semiconductor chip and chip mounting substrate, then performing thermocompression bonding. These sheet-like underfill materials are provided between the chip circuit face and chip mounting substrate, and are cured by predetermined means such as thermocompression or so to strongly adhere the chip circuit face and the chip mounting substrate.
Recently, so-called stud bumps with sharp tips are adopted as a form of the above bumps. When placing the sheet-like underfill material between the chip circuit face and the chip mounting substrate, the underfill material may break since the sheet-like underfill material is stretched due to the bump tips formed on the chip circuit face. When the underfill material is broken, it may cause the voids in the underfill material. Also, when adhering the sheet-like underfill material to the circuit face, air bubbles may be taken into the root part of the bumps depending on the form of the bumps thereby causing the voids. Further, when die-bonding via the sheet-like underfill material on the chip mounting substrate, the air bubbles may be taken in between the chip mounting substrate and the underfill material. Particularly, in recent years, patterned indents are formed sometimes by the wiring pattern on the chip mounting substrate surface which easily cause the voids. Also, although it depends on the type of the underfill materials, the voids may be formed due to the gas generated from the underfill materials during the curing step of the underfill materials.
If these voids remain within the underfill materials, it may become a starting point of the package crack. Hence, it is necessary to optimize the die-bonding condition to prevent the production of the voids. However, there are various package designs of the semiconductor device; further, the form, height and density of the bumps, and the surface form of the chip mounting substrate varies in a wide range, thus it is difficult to optimize the die-bonding condition.
In recent years, the IC cards have been widely used and further reduction of thickness thereof is demanded. Accordingly, it is now required that the thickness of the semiconductor chip, which has been about 350 μm, to be reduced to 20 to 100 μm or further less than this.
As a method to further reduce the thickness of the chip, patent document 5 (Japanese Patent Laid-Open No. H05-335411) discloses a process for producing the semiconductor chip wherein a groove of a predetermined depth is formed from a surface side of the wafer and, thereafter, the wafer is ground from a back face side. Such process is called “Dicing Before Grinding (DBG) process”. According to such DBG process, the production of the bump chip having extremely thin thickness is possible.
However, even when mounting such chip having the bumps, the above described problem of the voids production cannot be solved. Thus, a technique which removes the void upon its production is in demand.    [Patent document 1] JP-A No. H09-213741    [Patent document 2] JP-A No. H10-242208    [Patent document 3] JP-A No. H10-270497    [Patent document 4] JP-A No. 2002-118147    [Patent document 5] JP-A No. H05-335411